Atrenta announced that its 3D integration research program with IMEC has developed a planning and segmentation design process for heterogeneous 3D stacked chip assembly. Atrenta and IMEC also announced that they will showcase the design process jointly developed by DAC and 6~8 on June this year.

The design process combines the Spyglass entity 3D prototype tool developed by Atrenta, and the layout plan produced by the thermal and mechanical stress model developed by IMEC. Targeting areas include products for mobile and high-performance applications, imaging applications, stacked DRAM and solid-state drives (SSD), etc..

In the field of 3D design, there are several potential solutions for segmentation and interconnection, including silicon interpolator and grain orientation options. Other challenges include thermal and mechanical stresses that may arise during assembly and final configuration stages.

Limited by time and cost, it is almost impossible to explore different solutions through a comprehensive design. Therefore, it is of great potential to obtain feedback from virtual segmentation and prototyping before starting the design.

The key components of the 3D Atrenta design process are the thermal and mechanical model developed by IMEC, and the validated logic DRAM packaging parts.

The DAC in the display for routing congestion (routing congestion) 3D segmentation design stack; through silicon perforation (TSV) layout; back redistribution layer support, and can display the thermal profile function in the 3D plan, IMEC said.